As the processing speeds of computer systems have continually increased, there has been a corresponding need for faster and faster random access memory (RAM) devices. RAM devices, such as dynamic random access memory (DRAM) devices, are typically used as the main memory in computer systems. While DRAM devices have gotten faster over the years, the operating speeds of DRAM devices still lag behind the operating speeds of the processors which access the DRAM devices. Consequently, the relatively slow access and cycle times of DRAM devices slow down the processors, and create bottlenecks.
In response to the need for faster DRAM devices, synchronous dynamic random access memory (SDRAM) devices have been developed. SDRAM devices operate synchronously with the system clock which drives the processor that accesses the devices, with the input and output data of the SDRAM devices being synchronized to an active edge of the system clock. The initial SDRAM devices can be referred to as single data rate (SDR) SDRAM devices since their peak data rate is equal to the rate at which commands can be clocked into the devices. Single data rate SDRAMs are currently in widespread use.
To provide still faster DRAM devices, double date rate (DDR) SDRAM devices have been developed to provide twice the memory data bandwidth of SDR SDRAMs. The term DDR refers to the fact that the peak data rate is twice the rate at which commands can be clocked into the devices. DDR SDRAM devices typically allow commands to be entered on the positive edge of the system clock, and allow data transfers on both the rising and falling edges of the system clock to provide twice as much data as a SDR SDRAM device. DDR SDRAM devices typically employ a 2n-prefetch architecture, in which the internal data bus is twice the width of the external data bus. With this architecture, each read access cycle internal to the device provides two external data words, and each write access cycle internal to the device writes two combined external data words into the device.
In a purely synchronous system, output data (and capture of the output data by a memory controller) would be referenced to a common free-running system clock. In such a system, the maximum data rate would be reached when the sum of the output access time and the flight time approaches the bit time. Although the data rates could be increased by generating delayed clocks for early data launch and/or late data capture, these data rates would still be limited because these techniques do not account for the fact that the data valid window (i.e., the “data eye”) moves relative to any fixed clock signal due to changes in temperature, voltage or loading. To allow for even higher data rates, data strobe signals were added to DDR SDRAM devices. The data strobe signals are non-free-running signals driven by the device driving the data (i.e., the DDR SDRAM devices for READs, and the memory controller for WRITES). For READs, the data strobe signal is effectively an additional output having a predetermined pattern. For WRITEs, the data strobe signal is used by the SDRAM device as a clock in order to capture the corresponding input data.
Referring to FIG. 1, a data output timing diagram 10 for an existing DDR SDRAM device illustrates the relationship between the bidirectional data strobe signal and the data input/output signals for an exemplary READ operation (e.g., a four-word burst). In this example, the DDR SDRAM is assumed to be a 64 Mb×8 DDR SDRAM device available from Micron Technology, Inc. The CK and CK# signals represent differential system clock inputs, the DQS signal represents the data strobe signal, and the DQ signals represent the data input/output signals forming the device data bus. The DQS signal includes preamble, toggling, and postamble portions. The preamble portion provides a timing window for the receiving device to enable its data capture circuitry with a known/valid level present on the DQS signal. After the preamble portion, the DQS signal toggles in the toggling portion at the same frequency as the CK signal for the duration of the four-word data burst. Each high transition and each low transition of the DQS signal is associated with one data word, provided by the DQ signals driven by the DDR SDRAM device. In the postamble portion, the DQS signal goes low to indicate the end of the data burst to the receiving device. Thus, as shown, the data words are transmitted at twice the frequency of the system clock CK.
As illustrated in FIG. 1, the DQS signal is nominally edge-aligned with all of the DQ signals such that all of these output signals will transition at the output pins of the DDR SDRAM device at nominally the same time. The memory controller will then internally delay the DQS signal to the center of the received data eye upon capturing the data. The edge-alignment of the DQS and the DQ signals occurs because these output signals are all clocked out of the DDR SDRAM device by the same internal clock signal. Ideally, the DQS and DQ signals would all be perfectly aligned. However, as also shown in FIG. 1, the transitions of the DQS and DQ signals include a spread or distribution in time, which is due to both static effects (e.g., internal routing mismatch) and dynamic effects (e.g., data pattern and simultaneously switching outputs (SSO)). Even if critical signals are properly laid out on the die (e.g., using matching trace lengths), inherent differences in the package leadfingers' parasitics will contribute to this spread between the DQS and DQ signals, which is referred to as “output skew”. The output skew is specified by a parameter known as tDQSQ, which is the pin-to-pin skew measured at the DQS and DQ outputs of the device (i.e., the time between the transition of the DQS signal and the last DQ data valid). This skew (or |tDQSQ|) region is a region of uncertainty since at least one of the output signals is not valid. It is noted that the DQS signal may transition first, last, or somewhere in the middle of the DQ transition window. Maximum tDQSQ is currently specified as 500 psec.
The data word being read will be valid once the latest DQ signal in the group has transitioned, and will remain valid until the earliest DQ signal transitions as part of the next data word, or upon completion of the burst. The duration of this data valid window is specified by the tDV parameter, as shown in FIG. 1. The time between the transition of the DQS signal to the first DQ signal going non-valid is referred to as tQH (also shown). As is suggested by FIG. 1, output skew tDQSQ has an adverse impact on data valid window tDV. In particular, a relatively long output skew region will cause the data valid window to be relatively short. Since the memory controller can only capture data during the data valid window tDV, the output skew tDQSQ will also adversely impact the data capture operation.
Thus, although the addition of data strobe signals allowed for increased data rates, the operating speeds of existing DDR SDRAM devices are still limited by the output skew specified by the tDQSQ parameter. In particular, the output skew limits the operating speed (e.g., access and cycle times) of DDR SDRAM devices. Therefore, it would be desirable to provide a method and apparatus for reducing skew across the output data bus of a DDR SDRAM device, thereby enlarging the data eye for data capture by the memory controller. It would also be desirable to provide a method and an apparatus for reducing skew across multiple output signals in other memory device types, and other integrated circuit devices.